A combinational circuit containing the above and2 and nor2 components is shown in Figure 3. Repeat step 1) for a two-input NOR gate (entity name: nor2) shown in Figure 2(b). Print out the waveforms of the signals (a, b, c). Each pattern lasts for 10ns, and simulate for 4Ons. Use ModelSim to simulate its waveforms for input pattern sequence ab. Implement a two-input AND gate shown in Figure 2(a) with VHDL (entity name: and2 implement it with behavior model). ![]() Print out the ModelSim waveforms of all the signals (d, clk, q). Assume the input patterns are: clk=0 for t=0->10ns, 1 for t=10ns+20ns, clock period=20ns. ![]() Use ModelSim to simulate the D flip-flop. Write VHDL code (behavior model) to implement this positive-edge-triggered D flip-flop. (20") The block diagram of a positive-edge-triggered D flip-flop is shown in Figure 1.
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